Conference Papers
-
Cache Line Impact on 3D PDE Solvers
- Author(s)
- M. Kondo, M. Iwamoto, and H. Nakamura
- Conference
- ISHPC 2002
- Vol.
- LNCS 2327
- Pages
- 301–309
- Publisher
- Springer
- Publication Year
- 2002
- Date Presented
- Oct., 2002
Abstract
Because performance disparity between processor and main memory is serious, it is necessary to reduce off-chip memory accesses by exploiting temporal locality. Loop tiling is a well-known optimization which enhances data locality. In this paper, we show a new cost model to select the best tile size in 3D partial differential equations. Our cost model carefully takes account of the effect of cache line. We present performance evaluation of our cost models. The evaluation results reveal the superiority of our cost model to other cost models proposed so far.