研究成果

国際会議

  • Cache Line Impact on 3D PDE Solvers
    著者
    M. Kondo, M. Iwamoto, and H. Nakamura
    会議名
    ISHPC 2002
    LNCS 2327
    ページ
    301–309
    出版社
    Springer
    発行年
    2021
    発表日
    Oct., 2002
    Abstract

    Because performance disparity between processor and main memory is serious, it is necessary to reduce off-chip memory accesses by exploiting temporal locality. Loop tiling is a well-known optimization which enhances data locality. In this paper, we show a new cost model to select the best tile size in 3D partial differential equations. Our cost model carefully takes account of the effect of cache line. We present performance evaluation of our cost models. The evaluation results reveal the superiority of our cost model to other cost models proposed so far.