研究成果

Logic locking and eFPGA-based redaction are effective hardware design methods to thwart various threats that may happen when hardware designs containing intellectual properties (IPs) are outsourced to untrusted third-party fabrication facilities. Although a number of methods have been proposed, they focused on protecting an application-specific datapath IP and/or controller IP–protecting the datapath IP of general-purpose systems (such as processors) has not been studied yet even though they could also contain datapath IPs (e.g., custom operators added to the datapath through processor extension). Because applications executed on the processors may have different errortolerance when a locked (functionally-incorrect) datapath IP is used, the challenge here is to disable the processor's functionality for various applications (i.e., achieve the sufficient security level) while mitigating the circuit overheads induced by the protection. In this work, we present an eFPGA-based redaction method to protect a datapath IP in processors. Varying the number of bits and the operator for redaction, we quantitatively evaluate the effects on various applications with different error-tolerance and figure out appropriate eFPGA settings for protection from both the application and circuit overhead perspectives.