Publications

Logic locking and eFPGA-based redaction have emerged as promising security-by-design approaches for protecting hardware intellectual property (IP) in outsourced fabrication. While prior work has focused primarily on application-specific IPs, protecting general-purpose systems—such as processors with customized datapath extensions—remains underexplored. This setting is particularly challenging because workloads are unknown at design time and exhibit diverse tolerance to errors introduced by protection mechanisms, complicating the evaluation of effective IP protection. In this work, we propose PreLock, an eFPGA-based redaction method for securing processor datapath IPs. PreLock replaces selected datapath components with a compact eFPGA fabric, inducing pronounced functional and quality degradation across diverse workloads, including highly error-tolerant applications. We study three operator types and systematically examine the impact of configuration parameters and cost-related metrics that have been largely overlooked in prior studies. We further conduct comprehensive security analyses under multiple attack models to identify configurations that satisfy given security requirements while minimizing implementation cost. Based on these results, we derive principled strategies for configuration tuning and outline future directions toward more effective security-by-design solutions for hardware IP protection.