Implementation of Double Arbiter PUF and Its Performance Evaluation on FPGA
- T. Machida, D. Yamamoto, M. Iwamoto, and K. Sakiyama
- ASP-DAC 2015
- Jan. 19–22, 2015
Low uniqueness and vulnerability to machine-learning attacks are known as two major problems of Arbiter-Based Physically Unclonable Function (APUF) implemented on FPGAs. In this paper, we implement Double APUF (DAPUF) that duplicates the original APUF in order to overcome the problems. From the experimental results on Xilinx Virtex-5, we show that the uniqueness of DAPUF becomes almost ideal, and the prediction rate of the machine-learning attack decreases from 86% to 57%.